Meadow 6502 SBC User Document
Scott Chidester
Jan 15, 2003


Introduction

This user document details the use, specifications, design, and any other information of interest to the user, of the Meadow 6502 SBC (Single-Board Computer).

Overview

The Meadow 6502 SBC is a minimal computer system running on a single printed circuit board (PCB). It consists of a popular 8-bit microprocessor, 8K of read/write memory, 8K of read-only memory, and RS-232 communications for input/output. The SBC was built for recreation and learning--as a hobby project. It isn't intended for, nor is it probably suitable for, any other purpose.

This document is a detailed look at the use and operation of the SBC, and focuses on the MOS firmware revision 1.0.2, and the PCB revision 0.2b.

The Debug SBC

Often in this document there is a distinction between the debug SBC and the showcase SBC.

The debug SBC was the first board populated with parts and used to test and debug the whole Meadow 6502 system. It was outfitted with DIP sockets, modified with trace cuts, drilling, a blue wire, an extra resistor, etc., as the debug process unfolded.

The Showcase SBC

The showcase SBC was constructed to be shown as a final demonstration of the Meadow 6502 SBC. It was constructed with known good parts, no alterations to the PCB, and any bugs properly and cleanly accounted for. It is mounted in a clear plastic case to show off its parts, with a small, separate external board to provide some of the things the SBC needs to be a complete system (such as a power interface and a serial port interface). Additionally the showcase SBC has a power jack, female 9-pin serial cable, and a power switch.


The Design

Schematic

The schematic was drawn using a program called EAGLE Layout Editor. A parts library was created for most parts, and the schematic was drawn out with many parts in approximately their intended geographical location on the PCB.

Please note that it is NOT the final design; during final verification of the designed PCB, a few errors were found. While these errors were fixed on the PCB design before submission for prototyping, the changes did NOT make it back to this schematic. Here is a summary of most of the discrepancies between the schematic and the final PCB design:

Here is a link to the schematic: Schematic

Printed Circuit Board

The printed circuit board was also designed using EAGLE Layout Editor, which features an autorouter. After attempting to build a board using a Radio Shack PCB kit with etch-resist pens and decals, as well as an attempt at using iron-on laser printer sheets, it was decided to use ExpressPCB's prototype service. This required laying out the board traces and pads by hand, using ExpressPCB's layout software. The EAGLE Layout Editor program was then used simply to auto- route the address, data, and control signals; this information was then used to hand-route the entire PCB in ExpressPCB's layout editor. This proved more satisfactory anyway as traces could be more cleanly laid out.

This design was printed out and carefully gone over, trace by trace, to verify its correctness. As discussed below, even this final design was found to have an few errors after the boards were received and populated, however, no error proved too great to cause the circuit to be a failure. In fact, though some parts couldn't be mounted correctly (such as the voltage regulator), no blue wire or trace cuts were necessary.

Here is a link to a picture of the final PCB design; the red is the upper side of the PCB while the blue is the lower side, and magenta is, of course, where the two coincide: Board

Please see the photographs of the final populated boards and the discussion of location of parts below for actual parts placement.


The Board

Pictures of the debug SBC

Here are links to some high-resolution pictures of the debug SBC:

The top (click here for high-res version).

A side view (click here for high-res version).

The bottom (click here for high-res version).

Pictures of the showcase SBC

Here are links to some high-resolution pictures of the showcase SBC:

The top (click here for high-res version).

A side view (click here for high-res version).

The bottom (click here for high-res version).

Links to datasheets

Here are links to the PDF datasheets for most of the parts (particularly the ICs) used on the SBC. Note that most datasheets were found from the actual manufacturers of the parts used. Where they weren't, the parts's behaviors should be close to what the datasheets say, even if from different manufactureres. Of note is the 6502 itself; from the start, a Synertek datasheet was used, as an actual Synertek 6502 part was planned for use in the project. In fact, 6502 parts from Synertek, Rockwell, MOS Technologies, etc., should use the same mask set and should therefore be identical parts except where different manufacturing techniques alter their properties.

Synertek 6502

Motorola 6850

Hyundai 6264

ST 2764**

Atmel 28C64**

TI 7400

Philips 74HC393

TI MAX232

CTS Reeves clocks

Dallas DS1813

**The EPROMs are a problem; there is no guarantee that the write process for an Atmel 28C64 is the same as for the AMD 2864 used. Certainly the power usage is different.

Location and description of parts

All debug IC parts and oscillators are socketed on the debug SBC, to provide for testing of individual components or replacement of damaged parts due to a possibly incorrectly designed PCB (which proved to be a working design). Interestingly, the various DIP sockets arrived in different colors, some black, some blue, and some green. On the showcase SBC, all IC's with the exception of the ROM are directly soldered to the PCB, to provide a more attractive and compact-looking computer board. The ROM is still socketed, of course, to provide for removal and reprogramming by an external PROM programmer.

The Microprocessor

The 6502 is an 8-bit microprocessor designed in 1975 by MOS Technologies, which consisted of a few employees who recently left Motorola. It exists in two forms, the NMOS 6502 and the CMOS 65C02. Both come in black plastic packages.

The 6502 is located longitudially mounted on the left side of the PCB. The debug SBC uses a Rockwell NMOS 6502 while the showcase SBC uses a Rockwell CMOS 65C02.

The original NMOS version was used in various home computers such as all early Commodore computers (including variants in the very popular Commodore 64), early Apples (before MacIntosh), the famous Atari 2600 and Nintendo NES. The 6502 features 56 instructions, all with three-letter mnemonics, decimal or integer arithmetic, complex addressing modes, such as combinations indirect and indexed, a fast-access feature to the first 256 bytes of memory, IRQ/NMI, and other features. This version has a hardwired control unit. It also had a number of bugs, but most were of no consequence in normal use.

The CMOS version was designed later, and is still in production. It adds some instructions, fixes the bugs, and runs at negligible power consumption compared to the NMOS version. The control unit is microprogrammed. It is also fully static (the NMOS was dynamic and had to be clocked at a minimum frequency). It can be used as a direct replacement for the NMOS version, pin and software compatible.

Both processors directly address 64K of memory, have a non-multiplexed 8-bit databus, are semi-pipelined, and have instruction lengths variable from one to three bytes with execution ranging from two to seven clocks. It is little endian.

The 6502 expects certain addresses to be used in certain ways. The first 256 bytes of memory are called "zero page" and can be accessed using two byte instructions instead of three (the "zero page" part of the address is hidden in the opcode, which is the first instruction byte to be accessed; therefore only one more instruction byte is needed for the address within zero page). The next 256 bytes are always the stack. Through address decoding, the stack may be located anywhere (and since it grows downward, can even be located in systems with 256 bytes of RAM or less, as data tends to grow upward), but the processor always outputs an address at $0100 to $01FF to access it. Certain vectors for reset and interrupts are expected at the top six bytes of memory, locations $FFFA to $FFFF.

The clock used to drive the 6502 should be a 50% duty-cycle square wave at 1MHz or less (possibly down to about 100KHz before loss of state). The input clock is referred to as Phase 0 (zero), or PH0. Internally, two clocks are generated, whose high portions of their cycles do NOT overlap. One is Phase 1 (PH1), high during the first half of PH0, and Phase 2 (PH2), high during the second half. One PH0 cycle is the equivalent of one bus cycle. PH2 is the important signal for determining when external devices should either drive the data bus, or latch data from it.

The 6502 comes in a 40-pin dual-inline-package (DIP), with pins separated ten per inch, and 0.6 inches wide. In addition to the features mentioned, it also includes some other inputs and outputs. It outputs PH1, which is of little interest, and also PH2, for generating /WE and /OE control signals with R/W. Also output is a Synchronize (SYNC) signal which is asserted on the bus cycle that accesses the first (opcode) byte of an instruction. A Ready (RDY) input is provided to stop the processor's instruction processing, or allow it to continue. RDY may be deasserted before PH2 high to halt the bus cycle. This serves for single-stepping the processor, examining the bus with probes by hand, or particularly for adding wait states, allowing access to older, slow ROMs, who may need more than one bus cycle to produce valid data (external logic should hold RDY for one or more cycles). Finally, a Set-Overflow (SO) input is included. When deasserted, SO will set the V flag in the processor's status register; it is useful as perhaps a one-bit input in a minimal system, but also means that detecting true overflows from a subtraction instruction are difficult.

On this SBC, RDY is tied high to allow the 6502 to proceed unhindered. It is tied through a jumper, to allow single stepping. There is a row of four header pins near the 6502 (actually six, but this is talking about the right-most four). From left to right, they are: +5V, RDY, SYNC, GND. By placing a jumper between +5V and RDY, the 6502 behaves as always. However, an external circuit may be connected to these four pins (powered by the SBC, if needed), which can monitor the SYNC output and control the RDY input, allowing a push-button style single instruction step mode of operation. This feature is untested, so use with care. Since RDY cannot transition low during PH2 (doing so may cause the 6502 to freeze), the PH2 signal may be required. To the left of these four pins are two more pins that allow use of the SO input. It is also normally jumpered to +5V because it is an input.

The debug SBC includes a resistor soldered onto the underside of the PCB to passively pull the RDY input low if the jumper is removed. This was useful during debugging to allow a simple "freeze bus" mode by pulling the jumper. It is not guaranteed that the system produces a valid frozen bus and can recover from it, since there is a short period during the bus cycle that RDY must NOT transition low, and that time is impossible to determine when the jumper is pulled by hand.

The 6502 supplies a Non Maskable Interrupt Request (/NMI) input, which is tied to a pushbutton (the black button). When the pushbutton is open, a 3.3k ohm resistor passively deasserts this input. When the pushbutton is closed, the /NMI is pulled low. The intention of its use on this SBC is as a "panic" button; if a user's software program entered an endless loop, the operating system could drop into a debugging monitor when this button was pressed.

Likewise the 6502 /IRQ line is pulled high by a passive 3.3k ohm resistor. Both resistors are located to the right of the 6502 and to the left of the 7400; the /NMI pullup is to the left of the /IRQ pullup.

"Panic" and "Reset" pushbuttons are located on the very upper left of the SBC. The Reset button is to the left of the Panic button. Reset is the red button, while Panic is the black button. Momentary pushbuttons available from Radio Shack are used, but unfortunately the PCB was designed with holes that are too small. The debug SBC doesn't have these buttons mounted, but the showcase SBC does (the buttons's leads were filed down to fit, with acceptable results). See elsewhere for details of the reset circuit.

Memory

Both memory chips come in 28-pin DIPs, mounted longitudinally in the bottom middle of the board, to the lower right of the 6502. The 6264 is on the left, while the 2764/2864 is on the right. The 2764 pinout mostly matches the 6264, so routing these two chips's pins together is clean when they are side-by-side. The 6264 is plastic while the 2764/2864 are grey ceramic.

The 6264 is a CMOS static 8K memory. It has a non-multiplexed 8-bit data bus. It is a popular chip; these are manufactured by Hyundai.

The 2764/2864 is a UV erasable programmable read-only memory (EPROM), or an EEPROM (electrically erasable PROM). Several are available to be used in either the debug or the showcase SBC, while little data is provided for each. Generally they are NMOS (unless they have a 'C' in their part number, as in 27C64, in which case they'd be CMOS). These parts are made by Advanced Micro Devices (AMD). Documentation for these parts are representative; while most manufacturer's 2764s will behave similarly, no documentation from AMD specifically was found.

ACIA

The ACIA is a 24-pin DIP mounted longitudially to the bottom and right of the SBC. It is a purple-ceramic package with a gold lid and gold side-brazed pins.

The 6850 is a popular Motorola Asynchronous Communications Interface Adapter (ACIA) used as a Universal Asynchronous Receiver/Transmitter (UART). It is simple to use, and is bus-compatible with the 65xx family of chips. It has separate buffered transmit and receive registers, as well as three modem control lines (unused on this SBC) and interrupt logic. It is probably an NMOS device, though no documents confirm this.

The 6850 is accessed through four registers, two are read only and two are write only. Therefore there are only two addressable locations, and which register is read is further determined by the R/W input. There are two data registers (one for reading received data, and one for writing data to transmit) and one control register (write-only) and one status register (read-only). The control register selects baud rates, frame format, status of modem control output lines, etc. The status register reports the state of errors, interrupts, data buffers, and modem control input lines.

The 6850 is the only device on the SBC to drive the 6502's Interrupt Request (/IRQ) input. The output is open-drain, which means several devices may drive it high or low without fighting; a passive pullup resistor (3.3k ohms) serves to draw the line high (deasserted) unless one or more devices pulls the line low to request an interrupt.

The 6850 provides three modem control signals; one output (/RTS) and two inputs (/CTS and /DCD). Since these three inputs affect the normal operation of ACIA activities and are NOT general-purpose inputs, they are normally not used on the SBC. /RTS cannot be deasserted without disabling the transmitter interrupt. Regardless, it is provided on a jumper block above the 6850. Additionally, the /CTS input is provided on the jumper block, with a jumper to GND to permit normal operation (when deasserted, it disables transmit interrupts). /DCD is always tied low to prevent it from interfering with reception of data (it resets the ACIA).

RS-232

The RS-232 circuit is located above the 6850 and 2764, on the upper right of the board. It uses a MAX232 part in a 16-pin DIP, mounted latitudinally.

The MAX232 chip is used for translating two inputs and two outputs between TTL levels (around 0-5V range) to RS-232 levels (+/-12V). The part is designed by Maxim. The debug SBC used a device made by Texas Instruments, while the showcase SBC used a device made by Harris Semiconductor. It uses five radial electrolytic capacitors of 1uF each, and a single 5V power supply. On this SBC, only one set of input/output is translated, since the serial interface is three-wire (Tx/Rx/GND). The MAX232 is connected on one side to the 6850's receive/transmit data lines, and on the other to two pads for external connection to a computer via a 9-pin null-modem cable. On the debugging SBC, it was through a terminal block, while on the showcase SBC, two header pins were provided; since they are square, they work well for wirewrapping to a separate circuit board on which the connection to a serial cable can be made. The top pad is the receive input, and the bottom pad is the transmit output.

On the debug board, one electrolytic capacitor was mounted reverse-polarity, but seems to not be a problem. Everything is correctly polarized on the showcase SBC.

Bus Logic

The address and data bus are connected directly from the 6502 to the two memory chips and the ACIA. This is done, of course, through the many traces that occupy the top and bottom copper layers and plated-through via holes of the PCB. A15 and A14 are also used to drive address decoding logic (see Address Decoding).

A 7400 device (quad NAND gate) is used to develop control signals. The 7400 is a 14-pin package in the center top, longitudially mounted. The 7400 is a standard part, using TTL logic. It is made by Texas Instruments. Note that this is not a fancier part such as a 74LS00 or 74HC00, which include advanced technology to reduce power, increase speed, etc. It is sufficient for this circuit, however.

Since the 6850 is bus-compatible with the 6502, it's R/W and PH2 input (E) are connected directly to the 6502's corresponding outputs. It takes care of any other signal generation internally, except for CS logic (see Address Decoding).

The 6502's Read/Write output is connected directly to the 6850's R/W input, but goes through an inverter (NAND gate 1) and a NAND gate with phase 2 (NAND gate 2), to achieve the required timing signals for the 6264's /WE (write-enable) input.

From the 6502 timing diagram, everything is referenced to the phase 2 clock (PH2); when it goes low, it is considered the end of the bus cycle, and the various control/address/data signals are or are required to be valid for a few nanoseconds after PH2 low.

After PH2 low, the address (A) bus and R/W are valid for at least 30ns. However, according to the 6264 timing diagram, /WE needs to be deasserted at least 0ns before the A bus goes invalid. It appears that the A bus may go invalid before R/W (and thus /WE), causing data to be latched in the 6264 to an invalid address. So NANDing the inverted R/W line with PH2 caused the /WE line to deassert (causing latch of data) at least 30ns before the address bus became invalid, minus propagation delays through the two NAND gates. This new signal is called /PH2W; it goes low to indicate a write, but raises (deasserts) on PH2 low. The data bus remains valid for at least 60ns after PH2 low, so it is guaranteed to be valid when /WE is deasserted (causing latch of data).

R/W inverted (W/R) is fed directly to the output enable (/OE) of the 6264 and 2764. These could have been tied low, because assertion of /WE would have disabled them anyway. It was thought, though, that an accidental write (by software) to the EPROM would have caused a fight condition, since the 6502 and the 2764 would both be outputting data on the bus. The W/R signal would disable the 2764's output during a write to it (which would then simply be ignored). For completeness, W/R is also fed to the 6264, although it doesn't need to be. Please note that on the whole circuit schematic, this is not the case. The final SBC design submitted for prototyping has the circuit as shown below.

Showcase (unaltered) glue logic circuit

Speaking of writing to the 2764, provision is made for writing to a 2864 EEPROM. This is done through a jumper, which either connects the 2864's /WE line to the /PH2W line, or the 2764's /PGM pin to +5V. When jumpered to /PH2W, the 2864 should look like a 6264 to software, except perhaps it is allowed only one write every 1000us. When jumpered to +5V, the 2764's /P input will be always deasserted, since the device cannot be programmed in this circuit. Additionally when using a 2764 versus a 2864, a jumper is provided to tie the programming voltage pin, VPP, to +5V as required. When using a 2864, this pin should not be jumpered at all, as it may be used as an output to indicate programming status (RDY/BUSY) or a no-connect (NC).

It turns out that this isn't the "correct" way to do it. When documentation says that all bus timing is derived from PH2 of the 6502, it means it! On this revision of the system, once address and data signals come valid at the beginning of the clock cycle (PH2 low, PH1 high), the 6264 or 2764 output valid data. Thus when the 6502 is reading the 2764 (which it will appear to do in testing most of the time), the edges of data, address, control, etc. signals appear to transition on PH2 going low (the end of a bus cycle, and the start of a new bus cycle); the signals appear steady through the entire bus cycle. Another way to look at it is that the data bus appears to transition in phase with the address bus and R/W line

The 6850 data output however, appears to be valid only during the second half of the bus cycle, with the data bus retaining its values from the previous cycle (due to parasitic capacitance on the data bus).

The way it should work is that data signals on the bus should only be valid during the PH2 high half of the cycle. During PH2 low, the data bus should be off, and the signals should simply float; due to capacitive effects, the signals won't appear to change, float, or decay from their previous cycle. So the data bus should actually look like it is 180 out of phase with the address bus and R/W line, as in this diagram below (the shaded region of the data bus indicates a floating condition).

Address and data transitions relative to PH2

The method used on this revision happens to work anyway, as it should according to the timing diagrams. The 6850's half-cycle may be confusing, however. An alternative glue logic circuit was tried on the debug SBC; one 7400 input trace was cut and one blue wire was added to achieve the circuit below .

Debug (altered) glue logic circuit

This risks a race condition, but it appeared to be a small risk, and it brief spike of time; as PH2 raised, /OE would be high still until PH2 high caused it to transition low until the propagation through the W/R NAND gate completed. If the /WE spike is enough to trigger a write, then the 6264 would latch wrong data on every read of it. Again, it appears to work in practice on the debug SBC. On the showcase SBC, the circuit board is unmodified, and exhibits the bus behavior seen in the previous diagram.

A correct circuit can be achieved in the same three gates, without the race condition, as in the circuit diagram below. There is enough time between the R/W transitions and the PH2 transitions to prevent any race conditions. The 6502 specifies that data to read be valid for up to 10ns after PH2 low, but when /OE deasserts on the 6264, data may float immediately. However, there is some propagation delay through the NAND gates causing /OE to deassert later than PH2 low, and that capacitive effects keep the data bus steady during the ~500ns float time of the next cycle. In fact, the propagation through the glue logic for a plain 7400 is typically 8 to 11 ns, while a 74HC00 is similar. On the next design, this circuit is what will be used.

The best glue logic circuit

Address Decoding

The memory map for the SBC is shown below.
$0000-$1FFFRAM
$4000-$4001ACIA
$E000-$FFFFROM

A15 is used to select between high memory devices (only the EPROM), and low memory devices (the RAM and the ACIA). A14 is used to divide these two regions in to high and low parts. A15, along with an inverted A15 supplied from the 7400, (NAND gate number 3, with one input tied high) and A14 are enough to provide address decoding using the multiple chip enable pins on the memory and ACIA devices.

The 2764 ROM provides one active low /CS input. It is connected to /A15. Therefore, whenever A15 is high (addresses $8000 to $FFFF), the 2764 is always selected. Otherwise, it is always deselected.

The 6264 provides two chip selects, one active high and the other active low (/CS1 and CS2). /A15 is fed to CS2, which possibly selects the 6264 RAM only when accessing $0000 to $7FFF (A15 is low, so /A15 is high). When accessing $8000 to $FFFF, which is the ROM's region, the 6264 RAM is definitely disabled. /CS1 is fed with A14. Assuming A15 is low (accessing $0000 to $7FFF), when A14 is low (accessing $0000 to $3FFF), the 6264 RAM is selected. When A14 is high (accessing $4000 to $7FFF), the 6264 RAM is deselected.

The 6850 provides three chip selects, two active high, and one active low (CS0, CS1, /CS2). /CS2 is always tied low, so it cannot participate in deasserting the 6850. /A15 is fed to CS0, while A14 is fed to CS1. Therefore the selection behavior is like that for the 6264 RAM, except the 6850 is only enabled when accessing the top part of the low half of memory (addresses $4000 to $7FFF).

When the 6264 is selected, A13 is not an input to it. Therefore A13 is not a determining factor in what byte of RAM is addressed; it is a "don't care." A12-A0 will select the same RAM byte location whether A13 is high or low. When the 2764 is selected, both A14 and A13 are not connected to it, so they become don't cares. When the 6850 is selected, none of A13 through A1 are connected (it only has one address input, to select one of two addresses). The consequence of this is that each device has one or more shadow images of itself. An access to $4002 is the same as an access to $4000. An access to $A123 is the same as an access to $E123. In fact, the 6264 appears in the memory map twice, the 2764 appears four times, and the 6850 appears 16,384 times.

The memory map is then as follows:

$0000-$1FFF"Actual" RAM
$2000-$3FFFOne shadow of RAM
$4000-$4001"Actual" ACIA
$4002-$7FFF16,383 shadows of ACIA
$8000-$DFFFThree shadows of ROM
$E000-$FFFF"Actual" ROM

The positive consequence of this is that each memory location is accounted for. A read from any location will not result in a quasi-data byte caused by a floating bus, with no chip to drive it. The negative consequence is that buggy access at what should be invalid addresses by software may go undetected.

Reset

The reset circuit is located in the upper left of the board, just below two pushbuttons, and consists of a Dallas Semiconductor-designed and manufactured DS-1813 part, which comes in a transisor-like package.

Once the supply voltage has stabilized on power-up, the processor needs its reset input (/RES) asserted for at least six cycles (check the documents) to achieve a good reset. The DS-1813 reset part takes care of all of this in one simple three-pin transistor-like package. A pushbutton (red) is also provided for manual reset (showcase SBC only). The 6850 needs a programmed reset, which is the responsibility of software.

One bug on the board is that the pads for the DS-1813 indicate an intended part placement that is upsidedown from the actual circuit orientation. The chip should be mounted flat-side-up for proper operation.

Clocks

Two oscillators are provided on the SBC. They are each located on the left side of the board, below the reset circuit.

The 1MHz clock for the 6502 may be derived from a series of inverter gates (7404) with a crystal and some other components. Or, in the case of this SBC, an oscillator the size of an 8-pin DIP is used. Within this package, a good clean square 1MHz wave is generated and output for use by the 6502.

The oscillators are manufactured by CTS. They have an enable feature whose input pin is simply tied high.

The 6850's receiver/transmitter clock is generated by a similar 2.4576MHz crystal, which is fed to one half of a 74HC393 divide-by-sixteen counter. The output of this counter is at 153,600Hz, and is fed to both the Tx clock and the Rx clock inputs of the 6850. The 6850 is set for "divide by 16" mode, which reduces the baud rate to 9600. An optional divide-by-64 mode is available for 2400 baud. The 6850 can be operated in divide-by-1 mode, but then the receiver cannot center the bit sampling point. The other half of the 74HC393 is unused, and the input is tied high.

The 74HC393 appears to be manufactured by Philips, but that is not for sure.

The 6502 system clock (PH2) is available for testing on a header pin. Unfortunately the header pin is located too close to the /NMI pullup resistor, and is thus not provided on the showcase SBC.

Power

At least 7V should be connected to the SBC via the blue terminal block, positive on top, and negative on bottom (which serves as Ground, of course). One 7805 Voltage Regulator is used to reduce incoming voltage to 5V.

The power circuit has a few bugs. One is that when the board was designed, the holes for the 7805 were too small to fit an actual 7805. Drilling the holes out on the debugging SBC proved to merely uglify the board, thus the 7805 was used on a breadboard external to the SBC. On the showcase version, the 7805 socket input and output pads were connected with a wire, and the actual 7805 was located off-chip. Thus the showcase SBC needs exactly 5V from the external board. Had the 7805 been located on the SBC, there wouldn't have been room for a heat sink anyway--and the 7805 does get quite hot without it. While using the debug SBC, the 7805 had no heat sink, and functioned properly, but one is probably needed. Finally, a 1A 4001-type diode to protect against reverse voltage should have been included, since the 7805 is easily damaged by reversing the input voltage. On the showcase SBC, one is provided on the external board.

Along the perimeter of the SBC is the power bus. +5V is available in a thick trace on the top layer, while GND is available directly below it on the bottom layer. Parts needing power tap off of these traces at convenient places.

Capacitors are located at various places. There isn't room to give every chip its own dedicated 0.1uF capacitor, but the five provided are spaced appropriately. The debug SBC has large old-style ceramic disc capacitors while the showcase SBC has more attractive, smaller monolithic ceramic capacitors. One 10uF electrolytic axial type capacitor is located at the end of the power bus farthest from the supply, to smooth out any long power transients, but it isn't strictly necessary.

There was no room for a power switch on the debug SBC, but one is provided, mounted in the case, for the showcase SBC. It simply switches power at the jack.

One LED is provided as a power indicator. It is a rectangular pinkish red LED, with a frosted top. It is simply powered through a 330 ohm resistor from +5V to GND. It is not software controlled and cannot provide any indication that the computer is operating properly, only that power is applied to the circuit.

To power the debug SBC, provide exactly 5V. Positive terminal should be on the third terminal from the top of the block of four, and Negative on the fourth, bottom-most, terminal.

The showcase SBC has a 1/8 inch stereo headphone jack which can be used to plug in a power supply with an appropriate plug. The tip provides +7 to +30V while the sleeve provides ground. Some shorting may occur as the plug is inserted, so insert it in a rapid motion.

Power Consumption

These estimates are based on data sheets and may not reflect true power consumption. For example, the current draw of the 6264 is probably a maximum based on 70ns operation; at 1MHz, this is surely a lot less than the rated 50mA. Also, the 7400 draw is purely an (educated) guess, as is the draw from the 74HC393. It should also be noted that the power estimate does not include the voltage regulator, which probably uses a lot considering how hot it gets.

The following is an estimate of current draw of the debug SBC:

133 mANMOS 6502
60 mA6850
10 mA (50 mA max)6264 (CMOS)
50 mA (75 mA max)2764
20 mA7400
8 mAMAX232
1 mA74HC393
30 uADS-1819
5 mA * 2Oscillator
15 mALED Power indicator
300 mAEstimated Total

The showcase SBC's current draw is estimated below:

4 mACMOS 6502
160 mAEstimated Total

At 5V, the estimated total power usage of the debug SBC is 1.5 Watts, while the showcase SBC uses 0.8 Watts.


The Meadow Operating System

The Meadow Operating System (MOS) was developed as a minimal system to get the SBC up and running. "MOS" should not be confused with "MOS Technolgies," the company that designed the 6502; their name is probably an acronym for "Metal Oxide Semiconductor," the type of transistor that is in the 6502 (and almost all chips these days).

Overview

MOS provides for simple interrupt driven, full duplex buffered input and output via the 6850, as well as a command-line driven monitor program for viewing, setting, and executing the contents of memory. As of the "completion" point of this project (Fall 2002), it is that simple.

The MOS was written in 6502 assembler, of course, using a MOS Technologies- compatible assembler whose source code was free and compiles easily on any ANSI standard C. The source for it is located here: a65.zip (todo... links).

The following objectives (in order of priority) influenced the coding style for MOS:

Source Code

Here is a link to the source code: mos-1.0.2.a65

Details

Reset

The MOS first resets the 6502 by setting the stack pointer to $FF. It clears all registers (A, X, and Y), and then clears all flags in the status register. Then it disables interrupts. Some of this may be default behavior for a 6502 reset (is the stack pointer reset automatically?), but it is explicity done in MOS.

Next the MOS clears all 8K of RAM to zero. Following that, it initializes its variables, the 6850, and finally the ISR. A future version of MOS will not clear memory on a manual (pushbutton) reset by checking for initialized RAM signatures.

Then it proceeds to the prompt program, where it displays a banner and the prompt.

The I/O Driver

The I/O Driver is interrupt driven, with simple circular buffers, one for transmission and one for reception. Each buffer has a head pointer and a tail pointer. The interrupt service routine (ISR) is responsible for updating one pointer while the MOS user-callable function is responsible for the other. When both pointers match, the buffer is empty. When they don't match, one or more characters is in the buffer and needs to be processed.

When a character is received, the currently running program (whether user or MOS) is interrupted to place that character in a buffer (this interrupt is always enabled). Up to 255 characters can be received in this buffer, waiting to be processed by the MOS's GetCh function (any more beyond this are dropped silently). GetCh may be called by the MOS prompt, or by a user program through a function call. If a character is in the buffer (determined by comparing head and tail pointers), the routine returns immediately with the character; otherwise it waits in a loop for one to be inserted in the buffer by the ISR.

When a character or string is to be transmitted, the MOS or the user program calls PutCh or Puts. The routine then loads the string into the output buffer (up to 255 characters) to be sent asynchronously in the background while control returns to the calling program. When PutCh is called, it places the character in the buffer and enables the transmit-data-register-empty (TDRE) interrupt request (IRQ). If the 6850's transmit buffer is empty, an IRQ is made. The ISR checks to see if a character is in the 256-byte buffer, if so, it loads the character into the 6850. Otherwise, it disables the TDRE IRQ. If the buffer has several characters in it, the transmit ISR will be called as each one is transmitted to load the next one into the 6850. After the last one is transmitted, the ISR turns off the TDRE IRQ. In between each character, the processor may execute other code.

Here are some interesting facts: At 9600 baud, Puts can queue 18 characters for every one char that is transmitted. Also, the first few characters will cause several interrupts. The first is from the enabling of the TDRE IRQ after storing the first character to transmit in the circular buffer. After this character is loaded into the 6850 and this ISR returns, immediately a second interrupt occurs because the Tx buffer already emptied into the 6850 shift register for transmission, but up to now, only one character made it into the queue by this function, so the ISR simply turns off the TDRE IRW flag in the 6850. That returns control to Puts, where the second character is queued and the interrupt is re-enabled. That causes another interrupt to load the second character from the queue into the 6850. Now the 6850's Tx buffer is full, and it will be busy transmitting for some time before it is empty again; during this time Puts is free to loop through 16 characters before being interrupted again to load the third character from the queue. Puts and the ISR continue in this manner until Puts finishes copying everything to the queue. Puts can then return to the calling function to proceed while the ISR continues taking characters out of the queue every so often in the background. When the ISR exhausts the queue, it turns off the TDRE IRQ and doesn't run again. So Puts turns on interrupts while the ISR turns them off; Puts adds chars to the queue while ISR removes them; Puts handles the In pointer while the ISR handles the Out pointer. One doesn't modify the other's flags and variables (but may read them).

The Prompt

The MOS prompt provides three very important functions. First, it allows writing to memory from the command line. Second, it allows a report of that memory. Third, it allows execution of a program starting at a particular memory location. Other small things it provides are the ability to continue from an NMI event (the "panic" pushbutton), a small help screen, and a small demo.

This may seem terribly minimalist, but it does provide enough to at least download, upload, and execute software, from RAM. Download/upload can be achieved by using a terminal program's capture/send facilities.

Panic

Should MOS receive an NMI event (pushing of the "panic" button), it will reset the 6850 and buffers, dump the contents of the registers when the NMI was received, and re-enable the system, dropping into the MOS prompt for debugging. The stack will have six bytes reserved on it, storing a "stack frame" of the interrupted program. A pointer to this stack frame is kept in MOS, so should the user wish to continue the interrupted program, MOS can restore the state of the system and continue the program (except any pending I/O would be lost). Only one stack pointer is saved, so multiple NMIs without continue cannot be recovered--only the most recent. In fact, since the NMI handler uses six bytes of the stack, continued pressing of the panic button will use up all space on the stack. This is not a problem; the stack is circular, and after a dozen stack frames have been stored, eventually the first one will be overwritten.

Perhaps this will be improved in the future; only one NMI event will be allowed to interrupt a program (right now, NMI can interrupt a program, causing a drop into the MOS prompt, which can itself be interrupted, dropping into another MOS prompt, which itself can be interrupted...). Either the user aborts the program or continues it.

Structure

The first two bytes of MOS were intended initially to contain a checksum for verifying ROM contents, but this wasn't deemed necessary. Instead, the very beginning of MOS contains the text for the introduction banner. It is terminated by a zero, followed immediately by the character in DOS that signals EOF; if you use DOS's "type" command, you will see the prompt, and be spared the beeps and screen garbage from the ensuing machine language binary.

MOS ends up taking up only 2K of the 8K EPROM. The first 1K or so is string data, while the next 1K or so is 6502 machine language code.

There is a jump table for user programs at the end of MOS, just before the three vectors required by the 6502.

Jump Table

The jump table allows development of MOS while preventing the breaking of any software written for it, by allowing actual routines to be moved within the MOS address space, but keeping the jump table the same. Simply call these functions which are guaranteed to call the actual functions no matter where in MOS they're located. So far only four functions are provided as follows:

$FFEDCallGetCh
$FFF0CallPutCh
$FFF3CallGets
$FFF6CallPuts

NOTE: At this point, even these functions may be changed in the future, so backward compatibility is not guaranteed right now.

Internal Functions

So far there are only a few internal functions that are used by MOS to convert binary data to/from hexadecimal. These functions will be formalized at a later point and made available through the Jump Table.

Break Handler

At this time, BRK is not handled. If a user program has a BRK in it, the ISR should fall through with no action, and continue the program after the BRK (and the following, ignored byte).

Demonstration Program

One little demonstration program is included. Type 'd' at the prompt, and hit return, to see a "Hello, world!" program actually entered into the system and executed.

The demo works by placing MOS commands into the receiver buffer, as if they'd been received from the 6850, typed in by a user through a terminal. The sequence of commands are to enter the "Hello, world!" program and execute it. When the demo returns, the commands are echoed, parsed, and carried out dutifully by MOS.

Future Plans

The MOS prompt may be moved in the future to a more full-featured debugger, while other features such as a text editor, native assembler, disassembler, etc. are provided. Perhaps even a few games, etc.