Meadow 6502 SBC User Document
Jan 15, 2003
This user document details the use, specifications, design, and any other information of interest to the user, of the Meadow 6502 SBC (Single-Board Computer).
The Meadow 6502 SBC is a minimal computer system running on a single printed circuit board (PCB). It consists of a popular 8-bit microprocessor, 8K of read/write memory, 8K of read-only memory, and RS-232 communications for input/output. The SBC was built for recreation and learning--as a hobby project. It isn't intended for, nor is it probably suitable for, any other purpose.
This document is a detailed look at the use and operation of the SBC, and focuses on the MOS firmware revision 1.0.2, and the PCB revision 0.2b.
Often in this document there is a distinction between the debug SBC and the showcase SBC.
The debug SBC was the first board populated with parts and used to test and debug the whole Meadow 6502 system. It was outfitted with DIP sockets, modified with trace cuts, drilling, a blue wire, an extra resistor, etc., as the debug process unfolded.
The showcase SBC was constructed to be shown as a final demonstration of the Meadow 6502 SBC. It was constructed with known good parts, no alterations to the PCB, and any bugs properly and cleanly accounted for. It is mounted in a clear plastic case to show off its parts, with a small, separate external board to provide some of the things the SBC needs to be a complete system (such as a power interface and a serial port interface). Additionally the showcase SBC has a power jack, female 9-pin serial cable, and a power switch.
The schematic was drawn using a program called EAGLE Layout Editor. A parts library was created for most parts, and the schematic was drawn out with many parts in approximately their intended geographical location on the PCB.
Please note that it is NOT the final design; during final verification of the designed PCB, a few errors were found. While these errors were fixed on the PCB design before submission for prototyping, the changes did NOT make it back to this schematic. Here is a summary of most of the discrepancies between the schematic and the final PCB design:
Here is a link to the schematic: Schematic
The printed circuit board was also designed using EAGLE Layout Editor, which features an autorouter. After attempting to build a board using a Radio Shack PCB kit with etch-resist pens and decals, as well as an attempt at using iron-on laser printer sheets, it was decided to use ExpressPCB's prototype service. This required laying out the board traces and pads by hand, using ExpressPCB's layout software. The EAGLE Layout Editor program was then used simply to auto- route the address, data, and control signals; this information was then used to hand-route the entire PCB in ExpressPCB's layout editor. This proved more satisfactory anyway as traces could be more cleanly laid out.
This design was printed out and carefully gone over, trace by trace, to verify its correctness. As discussed below, even this final design was found to have an few errors after the boards were received and populated, however, no error proved too great to cause the circuit to be a failure. In fact, though some parts couldn't be mounted correctly (such as the voltage regulator), no blue wire or trace cuts were necessary.
Here is a link to a picture of the final PCB design; the red is the upper side of the PCB while the blue is the lower side, and magenta is, of course, where the two coincide: Board
Please see the photographs of the final populated boards and the discussion of location of parts below for actual parts placement.
Here are links to some high-resolution pictures of the debug SBC:
The top (click here for high-res version).
A side view (click here for high-res version).
The bottom (click here for high-res version).
Here are links to some high-resolution pictures of the showcase SBC:
The top (click here for high-res version).
A side view (click here for high-res version).
The bottom (click here for high-res version).
Here are links to the PDF datasheets for most of the parts (particularly the ICs) used on the SBC. Note that most datasheets were found from the actual manufacturers of the parts used. Where they weren't, the parts's behaviors should be close to what the datasheets say, even if from different manufactureres. Of note is the 6502 itself; from the start, a Synertek datasheet was used, as an actual Synertek 6502 part was planned for use in the project. In fact, 6502 parts from Synertek, Rockwell, MOS Technologies, etc., should use the same mask set and should therefore be identical parts except where different manufacturing techniques alter their properties.
CTS Reeves clocks
**The EPROMs are a problem; there is no guarantee that the write process for an Atmel 28C64 is the same as for the AMD 2864 used. Certainly the power usage is different.
All debug IC parts and oscillators are socketed on the debug SBC, to provide for testing of individual components or replacement of damaged parts due to a possibly incorrectly designed PCB (which proved to be a working design). Interestingly, the various DIP sockets arrived in different colors, some black, some blue, and some green. On the showcase SBC, all IC's with the exception of the ROM are directly soldered to the PCB, to provide a more attractive and compact-looking computer board. The ROM is still socketed, of course, to provide for removal and reprogramming by an external PROM programmer.
The 6502 is an 8-bit microprocessor designed in 1975 by MOS Technologies, which consisted of a few employees who recently left Motorola. It exists in two forms, the NMOS 6502 and the CMOS 65C02. Both come in black plastic packages.
The 6502 is located longitudially mounted on the left side of the PCB. The debug SBC uses a Rockwell NMOS 6502 while the showcase SBC uses a Rockwell CMOS 65C02.
The original NMOS version was used in various home computers such as all early Commodore computers (including variants in the very popular Commodore 64), early Apples (before MacIntosh), the famous Atari 2600 and Nintendo NES. The 6502 features 56 instructions, all with three-letter mnemonics, decimal or integer arithmetic, complex addressing modes, such as combinations indirect and indexed, a fast-access feature to the first 256 bytes of memory, IRQ/NMI, and other features. This version has a hardwired control unit. It also had a number of bugs, but most were of no consequence in normal use.
The CMOS version was designed later, and is still in production. It adds some instructions, fixes the bugs, and runs at negligible power consumption compared to the NMOS version. The control unit is microprogrammed. It is also fully static (the NMOS was dynamic and had to be clocked at a minimum frequency). It can be used as a direct replacement for the NMOS version, pin and software compatible.
Both processors directly address 64K of memory, have a non-multiplexed 8-bit databus, are semi-pipelined, and have instruction lengths variable from one to three bytes with execution ranging from two to seven clocks. It is little endian.
The 6502 expects certain addresses to be used in certain ways. The first 256 bytes of memory are called "zero page" and can be accessed using two byte instructions instead of three (the "zero page" part of the address is hidden in the opcode, which is the first instruction byte to be accessed; therefore only one more instruction byte is needed for the address within zero page). The next 256 bytes are always the stack. Through address decoding, the stack may be located anywhere (and since it grows downward, can even be located in systems with 256 bytes of RAM or less, as data tends to grow upward), but the processor always outputs an address at $0100 to $01FF to access it. Certain vectors for reset and interrupts are expected at the top six bytes of memory, locations $FFFA to $FFFF.
The clock used to drive the 6502 should be a 50% duty-cycle square wave at 1MHz or less (possibly down to about 100KHz before loss of state). The input clock is referred to as Phase 0 (zero), or PH0. Internally, two clocks are generated, whose high portions of their cycles do NOT overlap. One is Phase 1 (PH1), high during the first half of PH0, and Phase 2 (PH2), high during the second half. One PH0 cycle is the equivalent of one bus cycle. PH2 is the important signal for determining when external devices should either drive the data bus, or latch data from it.
The 6502 comes in a 40-pin dual-inline-package (DIP), with pins separated ten per inch, and 0.6 inches wide. In addition to the features mentioned, it also includes some other inputs and outputs. It outputs PH1, which is of little interest, and also PH2, for generating /WE and /OE control signals with R/W. Also output is a Synchronize (SYNC) signal which is asserted on the bus cycle that accesses the first (opcode) byte of an instruction. A Ready (RDY) input is provided to stop the processor's instruction processing, or allow it to continue. RDY may be deasserted before PH2 high to halt the bus cycle. This serves for single-stepping the processor, examining the bus with probes by hand, or particularly for adding wait states, allowing access to older, slow ROMs, who may need more than one bus cycle to produce valid data (external logic should hold RDY for one or more cycles). Finally, a Set-Overflow (SO) input is included. When deasserted, SO will set the V flag in the processor's status register; it is useful as perhaps a one-bit input in a minimal system, but also means that detecting true overflows from a subtraction instruction are difficult.
On this SBC, RDY is tied high to allow the 6502 to proceed unhindered. It is tied through a jumper, to allow single stepping. There is a row of four header pins near the 6502 (actually six, but this is talking about the right-most four). From left to right, they are: +5V, RDY, SYNC, GND. By placing a jumper between +5V and RDY, the 6502 behaves as always. However, an external circuit may be connected to these four pins (powered by the SBC, if needed), which can monitor the SYNC output and control the RDY input, allowing a push-button style single instruction step mode of operation. This feature is untested, so use with care. Since RDY cannot transition low during PH2 (doing so may cause the 6502 to freeze), the PH2 signal may be required. To the left of these four pins are two more pins that allow use of the SO input. It is also normally jumpered to +5V because it is an input.
The debug SBC includes a resistor soldered onto the underside of the PCB to passively pull the RDY input low if the jumper is removed. This was useful during debugging to allow a simple "freeze bus" mode by pulling the jumper. It is not guaranteed that the system produces a valid frozen bus and can recover from it, since there is a short period during the bus cycle that RDY must NOT transition low, and that time is impossible to determine when the jumper is pulled by hand.
The 6502 supplies a Non Maskable Interrupt Request (/NMI) input, which is tied to a pushbutton (the black button). When the pushbutton is open, a 3.3k ohm resistor passively deasserts this input. When the pushbutton is closed, the /NMI is pulled low. The intention of its use on this SBC is as a "panic" button; if a user's software program entered an endless loop, the operating system could drop into a debugging monitor when this button was pressed.
Likewise the 6502 /IRQ line is pulled high by a passive 3.3k ohm resistor. Both resistors are located to the right of the 6502 and to the left of the 7400; the /NMI pullup is to the left of the /IRQ pullup.
"Panic" and "Reset" pushbuttons are located on the very upper left of the SBC. The Reset button is to the left of the Panic button. Reset is the red button, while Panic is the black button. Momentary pushbuttons available from Radio Shack are used, but unfortunately the PCB was designed with holes that are too small. The debug SBC doesn't have these buttons mounted, but the showcase SBC does (the buttons's leads were filed down to fit, with acceptable results). See elsewhere for details of the reset circuit.
Both memory chips come in 28-pin DIPs, mounted longitudinally in the bottom middle of the board, to the lower right of the 6502. The 6264 is on the left, while the 2764/2864 is on the right. The 2764 pinout mostly matches the 6264, so routing these two chips's pins together is clean when they are side-by-side. The 6264 is plastic while the 2764/2864 are grey ceramic.
The 6264 is a CMOS static 8K memory. It has a non-multiplexed 8-bit data bus. It is a popular chip; these are manufactured by Hyundai.
The 2764/2864 is a UV erasable programmable read-only memory (EPROM), or an EEPROM (electrically erasable PROM). Several are available to be used in either the debug or the showcase SBC, while little data is provided for each. Generally they are NMOS (unless they have a 'C' in their part number, as in 27C64, in which case they'd be CMOS). These parts are made by Advanced Micro Devices (AMD). Documentation for these parts are representative; while most manufacturer's 2764s will behave similarly, no documentation from AMD specifically was found.
The ACIA is a 24-pin DIP mounted longitudially to the bottom and right of the SBC. It is a purple-ceramic package with a gold lid and gold side-brazed pins.
The 6850 is a popular Motorola Asynchronous Communications Interface Adapter (ACIA) used as a Universal Asynchronous Receiver/Transmitter (UART). It is simple to use, and is bus-compatible with the 65xx family of chips. It has separate buffered transmit and receive registers, as well as three modem control lines (unused on this SBC) and interrupt logic. It is probably an NMOS device, though no documents confirm this.
The 6850 is accessed through four registers, two are read only and two are write only. Therefore there are only two addressable locations, and which register is read is further determined by the R/W input. There are two data registers (one for reading received data, and one for writing data to transmit) and one control register (write-only) and one status register (read-only). The control register selects baud rates, frame format, status of modem control output lines, etc. The status register reports the state of errors, interrupts, data buffers, and modem control input lines.
The 6850 is the only device on the SBC to drive the 6502's Interrupt Request (/IRQ) input. The output is open-drain, which means several devices may drive it high or low without fighting; a passive pullup resistor (3.3k ohms) serves to draw the line high (deasserted) unless one or more devices pulls the line low to request an interrupt.
The 6850 provides three modem control signals; one output (/RTS) and two inputs (/CTS and /DCD). Since these three inputs affect the normal operation of ACIA activities and are NOT general-purpose inputs, they are normally not used on the SBC. /RTS cannot be deasserted without disabling the transmitter interrupt. Regardless, it is provided on a jumper block above the 6850. Additionally, the /CTS input is provided on the jumper block, with a jumper to GND to permit normal operation (when deasserted, it disables transmit interrupts). /DCD is always tied low to prevent it from interfering with reception of data (it resets the ACIA).
The RS-232 circuit is located above the 6850 and 2764, on the upper right of the board. It uses a MAX232 part in a 16-pin DIP, mounted latitudinally.
The MAX232 chip is used for translating two inputs and two outputs between TTL levels (around 0-5V range) to RS-232 levels (+/-12V). The part is designed by Maxim. The debug SBC used a device made by Texas Instruments, while the showcase SBC used a device made by Harris Semiconductor. It uses five radial electrolytic capacitors of 1uF each, and a single 5V power supply. On this SBC, only one set of input/output is translated, since the serial interface is three-wire (Tx/Rx/GND). The MAX232 is connected on one side to the 6850's receive/transmit data lines, and on the other to two pads for external connection to a computer via a 9-pin null-modem cable. On the debugging SBC, it was through a terminal block, while on the showcase SBC, two header pins were provided; since they are square, they work well for wirewrapping to a separate circuit board on which the connection to a serial cable can be made. The top pad is the receive input, and the bottom pad is the transmit output.
On the debug board, one electrolytic capacitor was mounted reverse-polarity, but seems to not be a problem. Everything is correctly polarized on the showcase SBC.
The address and data bus are connected directly from the 6502 to the two memory chips and the ACIA. This is done, of course, through the many traces that occupy the top and bottom copper layers and plated-through via holes of the PCB. A15 and A14 are also used to drive address decoding logic (see Address Decoding).
A 7400 device (quad NAND gate) is used to develop control signals. The 7400 is a 14-pin package in the center top, longitudially mounted. The 7400 is a standard part, using TTL logic. It is made by Texas Instruments. Note that this is not a fancier part such as a 74LS00 or 74HC00, which include advanced technology to reduce power, increase speed, etc. It is sufficient for this circuit, however.
Since the 6850 is bus-compatible with the 6502, it's R/W and PH2 input (E) are connected directly to the 6502's corresponding outputs. It takes care of any other signal generation internally, except for CS logic (see Address Decoding).
The 6502's Read/Write output is connected directly to the 6850's R/W input, but goes through an inverter (NAND gate 1) and a NAND gate with phase 2 (NAND gate 2), to achieve the required timing signals for the 6264's /WE (write-enable) input.
From the 6502 timing diagram, everything is referenced to the phase 2 clock (PH2); when it goes low, it is considered the end of the bus cycle, and the various control/address/data signals are or are required to be valid for a few nanoseconds after PH2 low.
After PH2 low, the address (A) bus and R/W are valid for at least 30ns. However, according to the 6264 timing diagram, /WE needs to be deasserted at least 0ns before the A bus goes invalid. It appears that the A bus may go invalid before R/W (and thus /WE), causing data to be latched in the 6264 to an invalid address. So NANDing the inverted R/W line with PH2 caused the /WE line to deassert (causing latch of data) at least 30ns before the address bus became invalid, minus propagation delays through the two NAND gates. This new signal is called /PH2W; it goes low to indicate a write, but raises (deasserts) on PH2 low. The data bus remains valid for at least 60ns after PH2 low, so it is guaranteed to be valid when /WE is deasserted (causing latch of data).
R/W inverted (W/R) is fed directly to the output enable (/OE) of the 6264 and 2764. These could have been tied low, because assertion of /WE would have disabled them anyway. It was thought, though, that an accidental write (by software) to the EPROM would have caused a fight condition, since the 6502 and the 2764 would both be outputting data on the bus. The W/R signal would disable the 2764's output during a write to it (which would then simply be ignored). For completeness, W/R is also fed to the 6264, although it doesn't need to be. Please note that on the whole circuit schematic, this is not the case. The final SBC design submitted for prototyping has the circuit as shown below.
Showcase (unaltered) glue logic circuit
Speaking of writing to the 2764, provision is made for writing to a 2864 EEPROM. This is done through a jumper, which either connects the 2864's /WE line to the /PH2W line, or the 2764's /PGM pin to +5V. When jumpered to /PH2W, the 2864 should look like a 6264 to software, except perhaps it is allowed only one write every 1000us. When jumpered to +5V, the 2764's /P input will be always deasserted, since the device cannot be programmed in this circuit. Additionally when using a 2764 versus a 2864, a jumper is provided to tie the programming voltage pin, VPP, to +5V as required. When using a 2864, this pin should not be jumpered at all, as it may be used as an output to indicate programming status (RDY/BUSY) or a no-connect (NC).
It turns out that this isn't the "correct" way to do it. When documentation says that all bus timing is derived from PH2 of the 6502, it means it! On this revision of the system, once address and data signals come valid at the beginning of the clock cycle (PH2 low, PH1 high), the 6264 or 2764 output valid data. Thus when the 6502 is reading the 2764 (which it will appear to do in testing most of the time), the edges of data, address, control, etc. signals appear to transition on PH2 going low (the end of a bus cycle, and the start of a new bus cycle); the signals appear steady through the entire bus cycle. Another way to look at it is that the data bus appears to transition in phase with the address bus and R/W line
The 6850 data output however, appears to be valid only during the second half of the bus cycle, with the data bus retaining its values from the previous cycle (due to parasitic capacitance on the data bus).
The way it should work is that data signals on the bus should only be valid during the PH2 high half of the cycle. During PH2 low, the data bus should be off, and the signals should simply float; due to capacitive effects, the signals won't appear to change, float, or decay from their previous cycle. So the data bus should actually look like it is 180 out of phase with the address bus and R/W line, as in this diagram below (the shaded region of the data bus indicates a floating condition).
Address and data transitions relative to PH2
The method used on this revision happens to work anyway, as it should according to the timing diagrams. The 6850's half-cycle may be confusing, however. An alternative glue logic circuit was tried on the debug SBC; one 7400 input trace was cut and one blue wire was added to achieve the circuit below .
Debug (altered) glue logic circuit
This risks a race condition, but it appeared to be a small risk, and it brief spike of time; as PH2 raised, /OE would be high still until PH2 high caused it to transition low until the propagation through the W/R NAND gate completed. If the /WE spike is enough to trigger a write, then the 6264 would latch wrong data on every read of it. Again, it appears to work in practice on the debug SBC. On the showcase SBC, the circuit board is unmodified, and exhibits the bus behavior seen in the previous diagram.
A correct circuit can be achieved in the same three gates, without the race condition, as in the circuit diagram below. There is enough time between the R/W transitions and the PH2 transitions to prevent any race conditions. The 6502 specifies that data to read be valid for up to 10ns after PH2 low, but when /OE deasserts on the 6264, data may float immediately. However, there is some propagation delay through the NAND gates causing /OE to deassert later than PH2 low, and that capacitive effects keep the data bus steady during the ~500ns float time of the next cycle. In fact, the propagation through the glue logic for a plain 7400 is typically 8 to 11 ns, while a 74HC00 is similar. On the next design, this circuit is what will be used.
The best glue logic circuit
The memory map for the SBC is shown below.
|$2000-$3FFF||One shadow of RAM|
|$4002-$7FFF||16,383 shadows of ACIA|
|$8000-$DFFF||Three shadows of ROM|
|133 mA||NMOS 6502|
|10 mA (50 mA max)||6264 (CMOS)|
|50 mA (75 mA max)||2764|
|5 mA * 2||Oscillator|
|15 mA||LED Power indicator|
|300 mA||Estimated Total|
|4 mA||CMOS 6502|
|160 mA||Estimated Total|